Hardware Design

• Make sure GPIO45 is not pulled high by external circuitry during power-up.
• In the R8 variants of ESP32-S3, the internal octal PSRAM uses GPIO33 to GPIO37, so those pins cannot be used for other functions.
• CHIP_PU must be delayed by 50 us during power-up. An external RC delay circuit is therefore required. A recommended starting point is 10 KΩ for the resistor and 1 uF for the capacitor.

• Make sure GPIO12 is not pulled high by external circuitry during power-up.
• If the ESP32 has internal or external PSRAM, GPIO16 requires a pull-up resistor.
• CHIP_PU must be delayed by 50 us during power-up, so an external RC delay circuit is required. A recommended starting point is 10 KΩ for the resistor and 1 uF for the capacitor.

• Make sure GPIO45 is not pulled high by external circuitry during power-up.
• CHIP_PU must be delayed by 50 us during power-up, so an external RC delay circuit is required. A recommended starting point is 10 KΩ for the resistor and 1 uF for the capacitor.

This usually happens because the new module has never been flashed before, so the flash does not contain a valid firmware image and the module cannot boot normally. In this state, the internal timer periodically resets the module every few seconds. Each reset reinitializes the USB Serial JTAG peripheral, so on the PC the USB serial port appears to connect, disconnect, and reconnect repeatedly.

For first-time USB flashing, pull the BOOT pin low before powering up so that the module enters download mode. The firmware can then be flashed normally. After flashing is complete, the USB serial port will stop reconnecting repeatedly.

When an ESP32 module is connected to Ethernet, the RMII interface uses fixed pins. Among them, GPIO0 serves both as the BOOT pin and as the RMII TX_CLK pin.

If the module and the PHY chip power up at the same time, GPIO0 may be pulled low, causing the module to enter download mode. Therefore, the power-up sequence between the ESP32 module and the PHY chip must be considered carefully.

It is recommended to use an ESP32 GPIO to control the PHY enable pin so that the PHY is not powered at exactly the same time as the module.

When connecting an SD card to ESP32 through SDIO, the recommended pins are GPIO2, GPIO4, and GPIO12 to GPIO15.

GPIO12 is a special strapping-related pin that affects the VDD_SPI output voltage during power-up. If GPIO12 is pulled high by external circuitry during boot, the SPI Flash supply may become abnormal and the chip may fail to start.

Disable the GPIO12 control of VDD_SPI in software, for example through eFuse or boot-time configuration, so the SD card interface does not interfere with the chip boot sequence.

ESP32-P4 uses the FB_DCDC pin to provide closed-loop feedback control for the external DCDC circuit. The output voltage of FB_DCDC is powered from the supply applied to VDD_DCDCC. If the external DCDC input supply differs from VDD_DCDCC, the reference voltages in the feedback loop will also differ, reducing regulation accuracy and stability.

Power the external DCDC input and the ESP32-P4 VDD_DCDCC pin from the same supply to avoid feedback regulation errors caused by mismatched input voltages.

Strapping pin timing has two important parameters:

• Setup time: the time required for the power rails to become stable before CHIP_PU/EN is driven high to activate the chip.
• Hold time: the time the chip needs to sample the Strapping values after CHIP_PU/EN is driven high. The pins become regular GPIOs after this interval, which is typically 1 ms to 3 ms.

To enter download mode, keep BOOT low while RESET transitions from low to high. Every Strapping pin has a latch. During system reset, the chip samples and stores the Strapping state, and the latched value remains unchanged until the chip is powered down or shut off. Changing the pin level alone does not update the stored state.

After changing a Strapping pin, toggle RESET so the chip samples the new state during reset. See the Strapping pin timing section in the ESP32-C3 Datasheet for the detailed timing parameters.