Audio & Video

ESP32, ESP32-S2, ESP32-S3, ESP32-C3, and similar SoCs can output audio directly through PWM (LEDC) or DAC, making it possible to connect a simple speaker or earphones for playback. The output volume is limited, so this is suitable mainly for basic applications.

In the official examples, a speaker can be connected directly to GPIOs such as GPIO25/26 on ESP32 and GPIO1/2 on ESP32-S2/S3/C3, with a 47 Ω series resistor. Example:
https://github.com/espressif/esp-iot-solution/blob/master/examples/audio/wav_player/README.md

Note that most ESP32 modules do not integrate a power amplifier. Directly driving a high-power speaker usually results in low volume. If higher volume or better sound quality is required, use a development board with an external audio amplifier or add an amplifier circuit around the module.

Yes. ES7210 is an input device and NS4168 is an output device. I2S can support input and output at the same time, and the data directions are opposite, while the other clock signals can be shared.

Only one channel needs to be created. On ESP32-S3, I2S supports full-duplex operation. See:
https://docs.espressif.com/projects/esp-idf/zh_CN/latest/esp32s3/api-reference/peripherals/i2s.html#id17

An ESP32-S3 module can directly connect to and drive an I2S digital microphone through the I2S interface.

For a PDM digital microphone, the ESP32-S3 can also use the PDM mode of the I2S peripheral and connect directly to the CLK and DATA signal lines.

An ESP32-S3 module cannot directly drive an analog microphone. An analog microphone requires an external Codec chip or another analog audio front-end circuit.

When ESP32-S3R2 drives an RGB565 interface display, keep PCLK at or below 11 MHz.

To improve the refresh rate, enable bounce buffer mode and turn on the following project configuration:

CONFIG_ESP32S3_DATA_CACHE_LINE_64B=y

A typical error log is:

I (1512) app_lcd: Install LCD driver of ek79007
I (1517) ek79007: version: 1.0.2
E (1700) sccb_i2c: s_sccb_i2c_transmit_receive_reg_a16v8(112): faled to transmit receive
E (1701) sc2336: Get sensor ID failed
E (1701) esp_video_init: failed to detect MIPI-CSI camera sensor with address=30
E (1708) app_video: Open video failed
E (1711) app_main: video cam open failed
I (1715) main_task: Returned from app_main()

video_lcd_display initializes the camera with the SC2336 driver by default and reads the sensor ID over SCCB/I2C. If the connected camera module does not use an SC2336 sensor, the sensor ID read fails, which then causes MIPI-CSI camera detection and video opening to fail.

Select the Camera Sensor Configuration that matches the actual sensor in menuconfig. See the video_lcd_display example documentation for the configuration path and procedure.

The current examples are adapted for SC2336. Using another sensor also requires the corresponding driver and parameter adaptation.

Symptoms:

The project uses ESP-IDF v5.5.4, and the peripheral circuitry has been adjusted for ESP32-P4 v3.2. The original MIPI DSI LCD works correctly with ESP32-P4 v1.x, but after changing the chip revision, the program triggers a task watchdog timeout at esp_lcd_new_dsi_bus(). The problem persists after changing CONFIG_HAL_WDT_USE_ROM_IMPL or upgrading ESP-IDF to v6.0.2.

E (7001) task_wdt: Task watchdog got triggered. The following tasks/users did not reset the watchdog in time:
E (7001) task_wdt:  - IDLE (CPU 0)
E (7001) task_wdt: Tasks currently running:
E (7001) task_wdt: CPU 0: main
E (7001) task_wdt: CPU 1: IDLE1
E (7001) task_wdt: Print CPU 0 (current core) backtrace

Backtrace: 0x4ff2ed24:0x4ff64b20 0x4ff23318:0x4ff64b50 0x4ff23366:0x4ff64b60 0x4ff2f192:0x4ff64b70 0x4ff3253c:0x4ff64b80 0x48081e04:0x4ff64bf0 0x4803b364:0x4ff64ca0 0x4803bad0:0x4ff64d50 0x480283c2:0x4ff64d60 0x48157d82:0x4ff64d80 0x4ff2eb40:0x4ff64d90 0x00000000:0x00000000

--- 0x4ff2ed24: vPortClearInterruptMaskFromISR at D:\work\code\esp-idf-v5.5.4\components\freertos\FreeRTOS-Kernel\portable\riscv\port.c:515
--- 0x4ff23318: crosscore_int_ll_trigger_interrupt at D:\work\code\esp-idf-v5.5.4\components\hal\esp32p4\include\hal\crosscore_int_ll.h:36
--- (inlined by) esp_crosscore_int_send at D:\work\code\esp-idf-v5.5.4\components\esp_system\crosscore_int.c:120
--- 0x4ff23366: esp_crosscore_int_send_yield at D:\work\code\esp-idf-v5.5.4\components\esp_system\crosscore_int.c:126
--- 0x4ff2f192: vPortYield at D:\work\code\esp-idf-v5.5.4\components\freertos\FreeRTOS-Kernel\portable\riscv\port.c:649
--- 0x4ff3253c: vTaskDelay at D:\work\code\esp-idf-v5.5.4\components\freertos\FreeRTOS-Kernel\tasks.c:1617
--- 0x48081e04: esp_lcd_new_dsi_bus at D:\work\code\esp-idf-v5.5.4\components\esp_lcd\dsi\esp_lcd_mipi_dsi_bus.c:97
--- 0x4803b364: ui_manager_display_new_ft8656 at D:\work\code\esp_test\esp32p4_camera\main\ui\ui_manager.c:324
--- 0x4803bad0: ui_manager_init at D:\work\code\esp_test\esp32p4_camera\main\ui\ui_manager.c:486
--- 0x480283c2: app_main at D:\work\code\esp_test\esp32p4_camera\main\main.c:247
--- 0x48157d82: main_task at D:\work\code\esp-idf-v5.5.4\components\freertos\app_startup.c:209
--- 0x4ff2eb40: vPortTaskWrapper at D:\work\code\esp-idf-v5.5.4\components\freertos\FreeRTOS-Kernel\portable\riscv\port.c:258

Cause:

After the ESP32-P4 chip revision is upgraded, the default clock source changes. The original MIPI DSI LCD initialization parameters do not match the newer chip revision, causing a timeout when the DSI bus is created.

Solution:

Check the initialization configuration against the latest ESP-IDF MIPI DSI LCD example, and adjust the parameters in the following structures according to the configuration requirements of the newer chip revision:

esp_lcd_dsi_bus_config_t
esp_lcd_dbi_io_config_t
esp_lcd_dpi_panel_config_t

Example: https://github.com/espressif/esp-idf/blob/bf4218a71fd5009ec6f9648e49721a5e0dc9ea35/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c#L229

Cause:

Driving a MIPI-DSI display requires high PSRAM bandwidth. Insufficient bandwidth, incorrect signal wiring, or a display lane configuration that does not match ESP32-P4's capabilities can result in a blank display without error logs.

Solution:

1. Check that the SPIRAM clock rate is configured to 200 MHz or above (CONFIG_SPIRAM_SPEED_200M=y).
2. Check that the physical connections between the display and the DSI data pins (DSI_DATAN0/DSI_DATAP0) and clock pins (DSI_CLKN/DSI_CLKP) are correct.
3. The ESP32-P4 DSI interface supports up to 2 lanes, with a maximum rate of 1.5 Gbps per lane. For displays configured for 4 lanes by default, such as ILI9881C or JD9365, change the initialization registers to switch to 2-lane mode.
4. Set lane_bit_rate_mbps to no more than 1500; a value of at least 480 is recommended. Calculate the actual value from the resolution, refresh rate, color depth, and lane count, and allow approximately 20% margin.